Digital Acoustics ESBx-110 Dokumentacja Strona 202

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Control Block Description
ADDvantage-32 PLUS
4-72
4.50 PEAK DETECT
1. Inputs
INP Analog
HLD Bit
RES Bit
POS Bit
2. Outputs
OUT Analog
3. Implementation
As long as the RES and HLD bits are low
OUT = the greater of Old OUT or INP (Greatest wins) if POS = 1
OUT = the least of Old OUT or INP (Greatest wins) if POS = 0
If the HLD bit is high, then OUT is held and INP is ignored.
If RES bit is high, OUT = 0.
RES and HLD are both level triggered bits.
RES has higher priority than HLD.
On powerup OUT = 0.
FIGURE 4-50. PEAK DETECT BLOCK
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